The present invention is directed generally to semiconductor devices and methods of fabrication and more particularly to three dimensional arrays of thin film transistors and method of fabrication.
Thin film transistors (TFTs) are utilized in various devices, such as a liquid crystal displays, static random access memories (SRAMs) and in nonvolatile memories. Conventional TFTs have a structure that is similar to conventional bulk metal oxide semiconductor field effect transistors (MOSFETs), except that TFTs are formed in a semiconductor layer that is located above an insulating substrate, such as a glass substrate or a semiconductor substrate that is covered by an insulating layer. The TFT device density on the substrate is usually lower than desired. The decreased device density increases the device cost, since fewer devices can be made on each substrate. PCT published application WO 02/15277 A2, which corresponds to U.S. application Ser. No. 09/927,648 filed on Aug. 13, 2002, incorporated herein by reference in its entirety, describes how three dimensional rail stack arrays of TFTs may be used utilized to decrease device density.
One preferred aspect of the present invention provides a semiconductor device, comprising a first field effect transistor, comprising (i) a first rail comprising a first channel, a first gate insulating layer and a first gate electrode, (ii) a first source region, and (iii) a first drain region. The device also comprises a second field effect transistor, comprising (i) a second rail comprising a second channel, a second gate insulating layer and a second gate electrode, (ii) a second source region, (iii) a second drain region, wherein the first rail comprises at least one of the second source region or the second drain region.
Another preferred aspect of the present invention provides a monolithic three dimensional array of field effect transistors, comprising (a substrate and a plurality of first rails disposed at a first height relative to the substrate in a first direction, wherein each of the plurality of first rails comprises a first heavily doped semiconductor layer of a first conductivity type. The array also comprises a plurality of second rails disposed in contact with the first rails, at a second height different from the first height, and in a second direction different from the first direction, wherein each of the plurality of second rails comprises a second heavily doped semiconductor layer of the first conductivity type, and a plurality of third rails disposed in contact with the second rails, in the first direction at a third height relative to the substrate such that the second rails are located between the first and the third rails, wherein each of the plurality of third rails comprises a third heavily doped semiconductor layer of the first conductivity type. Portions of the plurality of second rails comprise gate electrodes of a plurality of first field effect transistors and source or drain regions of a plurality of second field effect transistors.
Another preferred aspect of the present invention provides a monolithic three dimensional array of field effect transistors, comprising a substrate and a plurality of first rails disposed at a first height relative to the substrate in a first direction, wherein each of the plurality of first rails comprises a first heavily doped semiconductor layer of a first conductivity type. The array also comprises (c) a plurality of second rails disposed at a second height different from the first height, and in a second direction different from the first direction. Each of the plurality of second rails comprises a second lightly doped semiconductor channel layer of a second conductivity type located in contact with the first rails, a second heavily doped semiconductor layer of the first conductivity type, a second gate insulating layer between the second channel layer and the second heavily doped layer of the first conductivity type, and a second heavily doped semiconductor layer of the second conductivity type electrically connected to the second heavily doped semiconductor layer of the first conductivity type by a metal or a metal silicide layer. The array also comprises a plurality of third rails disposed in the first direction at a third height relative to the substrate. Each of the plurality of third rails comprises a third lightly doped semiconductor channel layer of the first conductivity type located in contact with the second heavily doped layer of the second conductivity type in the second rails, a third heavily doped semiconductor layer of the second conductivity type, a third heavily doped semiconductor layer of the first conductivity type electrically connected to the third heavily doped semiconductor layer of the first conductivity type by a metal or a metal silicide layer, and a third gate insulating layer between the channel layer and the third heavily doped layer of the second conductivity type.
Another preferred aspect of the present invention provides a semiconductor device, comprising a first field effect transistor of a first polarity and a second field effect transistor of a second polarity. A gate electrode of the first transistor is electrically connected to a source or drain of the second transistor without any lateral interconnects.
Another preferred aspect of the present invention provides a monolithic three dimensional memory array of field effect transistors, comprising a substrate and a plurality of first rails disposed at a first height relative to the substrate in a first direction, wherein each of the plurality of first rails comprises a first heavily doped semiconductor layer of a first conductivity type. The array also comprises a plurality of second rails disposed in contact with the first rails at a second height different from the first height, and in a second direction different from the first direction. Each of the plurality of second rails comprises a second heavily doped semiconductor layer of the first conductivity type, a second lightly doped semiconductor channel layer of the second conductivity type, and a second charge storage region located between the second heavily doped semiconductor layer and the second lightly doped semiconductor layer. The array further comprises a plurality of third rails disposed in the first direction at a third height relative to the substrate such that the second rails are located between the first and the third rails. Each of the plurality of third rails comprises a third heavily doped semiconductor layer of the first conductivity type, a third lightly doped semiconductor channel layer of the second conductivity type, and a third charge storage region located between the third heavily doped semiconductor layer and the third lightly doped semiconductor layer. The second lightly doped semiconductor layers in the second rails contact the first heavily doped semiconductor layers in the first rails. The third lightly doped semiconductor layers in the third rails contact the second heavily doped semiconductor layers in the second rails.
Another preferred aspect of the present invention provides a method of making a monolithic three dimensional field effect transistor array, comprising forming a plurality of first rails disposed at a first height relative to a substrate in a first direction, wherein each of the plurality of first rails comprises a first heavily doped semiconductor layer of a first conductivity type, forming a first insulating isolation layer over the first plurality of rails and patterning the first isolation layer to form a plurality of first openings exposing upper portions of first rails. The method further comprises forming a second lightly doped semiconductor layer of a second conductivity type over the patterned isolation layer such that transistor channel portions in the second lightly doped layer of the second conductivity type contact the first heavily doped layer of the first conductivity type through the first openings. The method further comprises forming a second gate insulating layer over the second lightly doped semiconductor layer of the second conductivity type, forming a second heavily doped semiconductor layer of the first conductivity type over the gate insulating layer, and patterning the second heavily doped layer of the first conductivity type, the second gate insulating layer and the second lightly doped layer of the second conductivity type to form a plurality of second rails extending in a second direction different from the first direction.
Another preferred aspect of the present invention provides a monolithic three-dimensional array of active devices comprising odd and even levels of field effect transistors, wherein odd levels comprise transistors of a first polarity, even levels comprise transistors of a second polarity and each transistor comprises a gate electrode, source, and drain, wherein the gate electrodes, sources, and drains of the transistors of at least two levels comprise polysilicon. Current flows between the source and the drain in a first direction through transistors of the first polarity and current flows between the source and the drain in a second direction not parallel to the first direction through transistors of the second polarity.
Another preferred aspect of the present invention provides a semiconductor device, comprising a first transistor having a gate electrode, source, channel, and drain oriented in a first direction, and a second transistor having a gate electrode, source, channel, and drain oriented in a second direction different from said first direction. The gate electrode of said first transistor and the source of said second transistor are disposed in a portion of a first rail.
Another preferred aspect of the present invention provides a semiconductor device a semiconductor device comprising a first rail, the first rail comprising a gate electrode of a first field effect transistor, and a source or drain of a second field effect transistor. The first transistor and the second transistor are oriented in non-parallel directions.